A non-volatile semiconductor memory array which can be widely used in various devices such as nitride read only memory, EEPROM, or Flash memory for retaining the memory even when the power is removed. FIG. 1A shows a top view of a conventional non-volatile memory array 10 which includes a grid of memory cells constructed by multi-layer process features. Invisible strips covered by a dielectric film 120 are the doped regions buried in the substrate and arranged as the source or drain for the memory cells. Conductive lines 140 are disposed in a parallel manner and orthogonal to the strips wherein the conductive lines 140 are usually called wordlines for the memory cells, and they are used to select a row of cells during the write or read operation. There is another conductive layer covered by the wordlines 140, and the conductive layer is arranged to act as the gate layer of each memory cell. Residues usually called stringer 160 are randomly formed along the sidewall of the dielectric pattern 120 after the etch step of conductive line 140. Ideally the gap between wordlines 140 should be free of any conductive material which may cause interference occurring between the wordlines.
For a better understanding of FIG. 1A, FIG. 1B is referred hereby to depict a cross-sectional view along line AA′ in FIG. 1A. The dielectric film 120 laid over the doped region 110 is located on the substrate 100 and provides isolation for adjacent gate layer 130. A charge trapping layer, which is illustrated as an ONO (oxide-nitride-oxide) stack 135 is disposed between the substrate 100 and the gate layer 130. FIG. 1C depicts a cross-sectional view along line BB′ and shows a region where there is supposed to be no gate layer 130 or wordline 140 existing.
FIGS. 2A to 2E-2 illustrate a portion of a conventional flow to produce the aforementioned memory array 10. Please also refer to FIG. 3A-3C while looking at the process flow. Steps of forming the ONO film 135 and the conductive gate layer 130 are skipped. FIG. 2A shows an etch step which is introduced to pattern the composite stack 130/135 into several strips wherein he composite stack 130/135 is etched to have a tapered sidewall. FIG. 2B shows the buried diffusion strips 110 are formed by an ion-implantation or a diffusion process. FIG. 3A is the corresponding top view of FIG. 2A. FIG. 2C illustrates that the dielectric film 120 is deposited to fill the gaps between the patterned composite stack 130/135 and an etch back or other planarization step is introduced to get a flat top surface. FIG. 3B is the corresponding top view of FIG. 2C. FIG. 2D (along AA′) following FIG. 2C-1 shows depositing the conductive film 140 which lays on the top of the composite stack 130/135. Finally, an etch step is adopted to cut the conductive films into several conductive lines 140 as shown in FIG. 3C. FIG. 1B and FIG. 1C respectively shows the cross section along line AA′ (wordline direction) and BB′. Apparently, according to the conventional design and process, the film stack 130/135 provides a site for the dielectric film 120 filling into the gaps to form a reversed tapered dielectric film 120. The conductive film 130 located on the side wall of the dielectric film 120 as shown in FIG. 1C may be difficult for the etch step to completely remove. Therefore, it is inevitable to leave conductive residues 160 more or less between the wordlines after the etch step. Hence, the interference such as cross talk caused by those conductive residues is a serious problem needs to be addressed.